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Tews introduces Spartan-6 AMC with FMC Module Slot in ruggedized version

The TAMC631 is a standard single Mid-Size or Full-Size AMC.1 Type 1 module providing a user configurable XC6SLX25T-2 or XC6SLX75T-2 Spartan-6 FPGA. The Spartan-6s PCIe Endpoint Block is connected to AMC port 4. The TAMC631 with XC6SLX75T FPGA also provides connections to AMC port 0 & 1.
For flexible front I/O solutions the TAMC631 provides a VITA 57.1 FMC Module slot with a low-pin count connector, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Spartan-6FPGA. The low-pin count interface includes one multi-gigabit link. The FPGA is connected to two banks of 128 Mbytes, 16 bit wide DDR3 SDRAM. The SRAM-interface uses the hardwired internal Memory Controller Blocks of the Spartan-6.
The FPGA is configured by a platform flash which is programmable via a JTAG header. The JTAG header also supports readback and real-time debugging of the FPGA design (using Xilinx ChipScope).A clock generator supplies up to three different clock frequencies between 5 kHz and 500 MHz to the FPGA. The clock generator settings are programmable via JTAG and are stored in an EEPROM. In addition two differential reference clocks are available from the FMC slot to the FPGA.
TEWS offers an FPGA Development Kit (FDK) which includes the TAMC631 User Manual, a well documented basic example design and an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TAMC631. It implements a DMA capable PCIe endpoint with interrupt support, register mapping, DDR3 memory access and basic I/O to the FMC slot. It comes as a Xilinx ISE project with source code and as ready-to-download bitstream.